1. Technical Field
The present invention relates to a non-volatile storage element including control gates and manufacturing method thereof.
2. Related Art
A structure for a twin MONOS (Metal Oxide Nitride Oxide Silicon) memory cell structure of the related art is disclosed in Japanese Laid-open patent publication NO. 2002-230988. A twin MONOS memory cell contains two control gates formed either side of a single word gate, two nitride storage members formed underneath, and underneath which two diffusion regions are formed. With a memory cell configured in this manner, it is possible to form two data saving regions at one cell, and achieve two bits per cell.
However, with this kind of twin MONOS memory cell of the related art, a word gate is formed between two control gates. Further, for example, an ONO film constituting a data saving region is formed at a word gate side wall. As a result, memory cell structure becomes larger by just the portion of the word gate width and film thickness of the ONO film, putting a limit on fine detailing.
A non-volatile memory element of a structure that does not include a word gate is disclosed in Japanese Laid-open patent publication NO. 2003-17600. FIG. 20 is a cross-sectional view showing a configuration for a cell disclosed in Japanese Laid-open patent publication NO. 2003-17600. Here, an EEPROM (Electrically Erasable and Programmable Memory) element contains a semiconductor substrate 60, first and second conductive gates 71, 72 mutually facing and respectively formed on first and second channel regions 83, 84, first and second insulating films (ONO films) 70, 65 respectively formed below and between the first and second conductive gates 71, 72 on the substrate 60, and first and second connecting regions 81, 82. The first and second connecting regions 81, 82 are of a second conductive type and limiting the first and second channel regions 83, 84 formed on the substrate 60 so as to overlap with the first and second conductive gates 71, 72 at a space of the substrate 60 there between. A non-volatile memory element of this configuration is configured in such a manner that two memory cells are connected consecutively between a pair of bit lines so as to constitute one unit cell. Each unit cell then stores two bits of data one bit at a time at each memory cell.
The non-volatile memory element disclosed in Japanese Laid-open patent publication NO. 2003-17600 is formed in the following manner. First, a pad oxidation film and a thick nitride film are sequentially formed on the semiconductor substrate. Next, the nitride film and the pad oxidation film are patterned using a photo-etching method, and windows are formed in such a manner as to expose predetermined portions of the substrate. After this, an oxidation film, nitride film, and oxidation film are formed on the nitride film containing a window in that order, with a polysilicon film being deposited on top. After this, the polysilicon film, oxidation film, nitride film, and oxidation film are etched back, so as to form a spacer-shaped first conductive gate and an ONO film composed of the oxidation film, nitride film and oxidation film in the side wall of the nitride film within the window. After this, the nitride film and pad oxidation film are removed. As a result, a first conductive gate 71 and a first insulating film (ONO film) 70 are formed as shown in FIG. 20.
Next, an oxidation film, a nitride film, and an oxidation film are deposited sequentially on the substrate surface, with a polysilicon film then being deposited on top. After this, the polysilicon film, the oxidation film, the nitride film and the oxidation film are etched back. As a result, the second conductive gate 72 and the second insulating film (ONO film) 65 facing the first conductive gate 71 formed previously are formed.
Because the non-volatile memory element disclosed in Japanese Laid-open patent publication NO. 2003-17600 is formed using the manufacturing procedure described above, it is inevitable that each ONO film is formed in a continuous manner so as to span from a bottom part of a conductive gate to a side-wall between two conductive gates. Two ONO films are therefore arranged between two conductive gates. It is therefore not possible to shorten the distance between two conductive gates to not less than the distance of two ONO films, and fine-detailing of a non-volatile memory element is therefore restricted.
Further, because the nitride film constituting an electron trapping film within the ONO film is formed so as to span from a bottom part of a conductive gate to a side wall, electrons trapped within the nitride film are dispersed within the nitride film, electron density is diluted, and retention characteristics deteriorate.
It is also necessary to form conductive gates for each unit cell one at a time. The manufacturing procedure is therefore complex and the number of manufacturing steps is substantial. Moreover, the two ONO films formed below the two conductive gates are made by a separate process and this presents the problem that variations occur in the characteristics of these films.